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never stop thinking. hys72d32300gbr?[5/6/7]?b hys72d643[00/20]gbr?[5/6/7]?b hys72d128320gbr?[5/6/7]?b 184 - pin registered double data rate sdram modules reg dimm ddr sdram data sheet, rev. 1.1, apr. 2004 memory products
edition 2004-04 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hys72d32300gbr?[5/6/7]?b hys72d643[00/20]gbr?[5/6/7]?b hys72d128320gbr?[5/6/7]?b 184 - pin registered double data rate sdram modules reg dimm ddr sdram data sheet, rev. 1.1, apr. 2004 memory products
template: mp_a4_v2.2_2003-10-07.fm hys72d32300gbr?[5/6/7]?b hys72d643[00/20]gbr?[5/6/7]?b hys72d128320gbr?[5/6/7]?b hys72d643[00/20]gbr?[5/6/7]?b hys72d128320gbr?[5/6/7]?b revision history: rev. 1.1 2004-04 previous version: rev. 1.0 2003-12 page subjects (major changes since last revision) 21,22 registerd and pll current added we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
data sheet 5 rev. 1.1, 2004-04 hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 spd contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6 application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table of contents
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules overview data sheet 6 rev. 1.1, 2004-04 10102003-01e2-hpa8 1 overview 1.1 features 184-pin registered 8-byte dual-in-line ddr sdram module for ?1u? pc, workstation and server main memory applications one rank 32m 72, 64m 72 and two ranks 64m 72, 128m 72 organization jedec standard double data rate synchronous drams (ddr sdram) with a single + 2.5 v ( 0.2 v) power supply and a single + 2.6 v ( 0.1 v) power supply for ddr400 built with 256-mbit ddr-i sdrams in p-tfbga-60-1 packages programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh all inputs and outputs sstl_2 compatible re-drive for all input signals using register and pll devices. serial presence detect with e 2 prom low profile modules form factor: 128.95 mm 28.58 mm 4.00 mm 133.35 mm 30.48 mm (1.2?) 4.00 mm (6.80 mm with stacked components) jedec standard reference layout for one rank 256mb and 512mb, two ranks 512mb and 1gbyte: pc2700 registered dimm raw cards a,b,c,d gold plated contacts 1.2 description the hys72d[32/64/128]3[00/20]gbr are low profile versions of the standard registered dimm modules with less/equal 1.2? inch (30.48 mm) height for 1u server applications. the low profile dimm versions are available as 32m 72 (256mb), 64m 72 (512mb) and 128m 72 (1 gb). the memory array is designed with double data rate synchronous drams for ecc applications. all control and address signals are re-driven on the dimm using register devices and a pll for the clock distribution. this reduces capacitive loading to the system bus, but adds one cycle to the sdram timing. a variety of decoupling capacitors are mounted on the pc board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. table 1 performance part number speed code -5 ? 6-7 unit speed grade component ddr400b ddr333b ddr266a ? module pc3200-3033 pc2700?2533 pc2100-2033 ? max. clock frequency @cl3 f ck3 200 166 ? mhz @cl2.5 f ck2.5 166 166 143 mhz @cl2 f ck2 133 133 133 mhz
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules overview data sheet 7 rev. 1.1, 2004-04 10102003-01e2-hpa8 note: all ?product type? end with a place code designating the silicon-die revision. reference information available on request. example: hys72d64300gr-5-b, indicating rev. c dies are used for sdram components. the ?compliance code? is printed on the module labels describing the speed sort (for example ?pc2700?), the latencies and spd code definition (for example ?20330? means cas latency of 2.0 clocks, rcd 1) latency of 3 clocks, row precharge latency of 3 clocks, and jedec spd code definiton version 0), and the raw card used for this module. table 2 ordering information type compliance code description sdram technology pc3200 (cl = 3, t rp = t rcd = 3 at t ck = 5ns) hys72d32300gbr?5?b pc3200r-30330-a one rank 256 mb registered dimm 256 mbit ( 8) hys72d64300gbr?5?b pc3200r-30330-c one rank 512 mb registered dimm 256 mbit ( 4) hys72d64320gbr?5?b pc3200r-30330-b two ranks 512 mb registered dimm 256 mbit ( 8) hys72d128320gbr?5?b pc3200r-30331-d two ranks 1 gb registered dimm 256 mbit ( 4) pc2700 (cl = 2.5, t rp = t rcd = 3 at t ck = 6ns) hys72d32300gbr?6?b pc2700r-25330-a one rank 256 mb registered dimm 256 mbit ( 8) hys72d64300gbr?6?b pc2700r-25330-c one rank 512 mb registered dimm 256 mbit ( 4) hys72d64320gbr?6?b pc2700r-25330-b two ranks 512 mb registered dimm 256 mbit ( 8) hys72d128320gbr?6?b pc2700r-25330-d two ranks 1 gb registered dimm 256 mbit ( 4) pc2100 (cl = 2, t rp = t rcd = 3 at t ck = 7.5ns) hys72d32300gbr?7?b pc2100r-20330-a one rank 256 mb registered dimm 256 mbit ( 8) hys72d64300gbr?7?b pc2100r-20330-c one rank 512 mb registered dimm 256 mbit ( 4) hys72d64320gbr?7?b pc2100r-20330-b two ranks 512 mb registered dimm 256 mbit ( 8) hys72d128320gbr?7?b pc2100r-20330-d two ranks 1 gb registered dimm 256 mbit ( 4) 1) rcd: row-column-delay
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules pin configuration data sheet 8 rev. 1.1, 2004-04 10102003-01e2-hpa8 2 pin configuration the pin configuration of the registered ddr sdram dimm is listed by function in table 3 (184 pins). the abbreviations used in columns pin and buffer type are explained in table 4 and table 5 respectively. the pin numbering is depicted in figure 1 . table 3 pin configuration of rdimm pin# name pin type buffer type function clock signals 137 ck0 i sstl clock signal 138 ck0 isstl complement clock 21 cke0 i sstl clock enable rank 0 111 cke1 i sstl clock enable rank 1 note: 2-rank module nc nc sstl note: 1 -rank module control signals 157 s0 isstl chip select of rank 0 158 s1 isstl chip select of rank 1 note: 2-ranks module nc nc ? note: 1-rank module 154 ras isstl row address strobe 65 cas isstl column address strobe 63 we isstl write enable 10 reset ilv- cmos register reset forces registered inputs low note: for detailed description of the power up and power management see the application note at the end of data sheet address signals 59 ba0 i sstl bank address bus 1:0 52 ba1 i sstl 48 a0 i sstl address bus 11:0 43 a1 i sstl 41 a2 i sstl 130 a3 i sstl 37 a4 i sstl 32 a5 i sstl address bus 11:0 125 a6 i sstl address bus 11:0 29 a7 i sstl 122 a8 i sstl 27 a9 i sstl 141 a10 i sstl ap i sstl 118 a11 i sstl 115 a12 i sstl address signal 12 note: module based on 256 mbit or larger dies nc nc ? note: 128 mbit based module 167 a13 i sstl address signal 13 note: 1 gbit based module nc nc ? note: module based on 512 mbit or smaller dies table 3 pin configuration of rdimm (cont?d) pin# name pin type buffer type function
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules pin configuration data sheet 9 rev. 1.1, 2004-04 10102003-01e2-hpa8 data signals 2 dq0 i/o sstl data bus 63:0 4 dq1 i/o sstl 6 dq2 i/o sstl 8 dq3 i/o sstl 94 dq4 i/o sstl 95 dq5 i/o sstl 98 dq6 i/o sstl 99 dq7 i/o sstl 12 dq8 i/o sstl 13 dq9 i/o sstl 19 dq10 i/o sstl 20 dq11 i/o sstl 105 dq12 i/o sstl 106 dq13 i/o sstl 109 dq14 i/o sstl 110 dq15 i/o sstl 23 dq16 i/o sstl 24 dq17 i/o sstl 28 dq18 i/o sstl 31 dq19 i/o sstl 114 dq20 i/o sstl 117 dq21 i/o sstl 121 dq22 i/o sstl 123 dq23 i/o sstl 33 dq24 i/o sstl 35 dq25 i/o sstl 39 dq26 i/o sstl 40 dq27 i/o sstl 126 dq28 i/o sstl 127 dq29 i/o sstl 131 dq30 i/o sstl 133 dq31 i/o sstl 53 dq32 i/o sstl 55 dq33 i/o sstl 57 dq34 i/o sstl 60 dq35 i/o sstl 146 dq36 i/o sstl 147 dq37 i/o sstl table 3 pin configuration of rdimm (cont?d) pin# name pin type buffer type function 150 dq38 i/o sstl data bus 63:0 151 dq39 i/o sstl 61 dq40 i/o sstl 64 dq41 i/o sstl 68 dq42 i/o sstl 69 dq43 i/o sstl 153 dq44 i/o sstl 155 dq45 i/o sstl 161 dq46 i/o sstl 162 dq47 i/o sstl 72 dq48 i/o sstl 73 dq49 i/o sstl 79 dq50 i/o sstl 80 dq51 i/o sstl 165 dq52 i/o sstl 166 dq53 i/o sstl 170 dq54 i/o sstl 171 dq55 i/o sstl 83 dq56 i/o sstl 84 dq57 i/o sstl 87 dq58 i/o sstl 88 dq59 i/o sstl 174 dq60 i/o sstl 175 dq61 i/o sstl 178 dq62 i/o sstl 179 dq63 i/o sstl 44 cb0 i/o sstl check bits 7:0 45 cb1 i/o sstl 49 cb2 i/o sstl 51 cb3 i/o sstl 134 cb4 i/o sstl 135 cb5 i/o sstl 142 cb6 i/o sstl 144 cb7 i/o sstl 5 dqs0 i/o sstl data strobes 8:0 note: see block diagram for corresponding dq signals 14 dqs1 i/o sstl 25 dqs2 i/o sstl 36 dqs3 i/o sstl 56 dqs4 i/o sstl 67 dqs5 i/o sstl table 3 pin configuration of rdimm (cont?d) pin# name pin type buffer type function
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules pin configuration data sheet 10 rev. 1.1, 2004-04 10102003-01e2-hpa8 78 dqs6 i/o sstl data strobes 8:0 86 dqs7 i/o sstl 47 dqs8 i/o sstl 97 dm0 i sstl data mask 0 note: 8 based module dqs9 i/o sstl data strobe 9 note: 4 based module 107 dm1 i sstl data mask 1 note: 8 based module dqs10 i/o sstl data strobe 10 note: 4 based module 119 dm2 i sstl data mask 2 note: 8 based module dqs11 i/o sstl data strobe 11 note: 4 based module 129 dm3 i sstl data mask 3 note: 8 based module dqs12 i/o sstl data strobe 12 note: 4 based module 149 dm4 i sstl data mask 4 note: 8 based module dqs13 i/o sstl data strobe 13 note: 4 based module 159 dm5 i sstl data mask 5 note: 8 based module dqs14 i/o sstl data strobe 14 note: 4 based module 169 dm6 i sstl data mask 6 note: 8 based module dqs15 i/o sstl data strobe 15 note: 4 based module 177 dm7 i sstl data mask 7 note: 8 based module dqs16 i/o sstl data strobe 16 note: 4 based module 140 dm8 i sstl data mask 8 note: 8 based module dqs17 i/o sstl data strobe 17 note: 4 based module table 3 pin configuration of rdimm (cont?d) pin# name pin type buffer type function eeprom 92 scl i cmos serial bus clock 91 sda i/o od serial bus data 181 sa0 i cmos slave address select bus 2:0 182 sa1 i cmos 183 sa2 i cmos power supplies 1 v ref ai ? i/o reference voltage 184 v ddspd pwr ? eeprom power supply 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 v ddq pwr ? i/o driver power supply 7, 38, 46, 70, 85, 108, 120, 148, 168 v dd pwr ? power supply table 3 pin configuration of rdimm (cont?d) pin# name pin type buffer type function
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules pin configuration data sheet 11 rev. 1.1, 2004-04 10102003-01e2-hpa8 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 v ss gnd ? ground plane other pins 82 v ddid ood v dd identification note: pin in tristate, indicating v dd and v ddq nets connected on pcb 9, 16, 17, 71, 75, 76, 90, 101, 102, 103, 113, 163, 173 nc nc ? not connected pins not connected on infineon rdimm?s table 3 pin configuration of rdimm (cont?d) pin# name pin type buffer type function table 4 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nu not usable (jedec standard) nc not connected (jedec standard) table 5 abbreviations for buffer type abbreviation description sstl serial stub terminalted logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or.
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules pin configuration data sheet 12 rev. 1.1, 2004-04 10102003-01e2-hpa8 figure 1 pcb with pin connector pin 93 pin 184 pin 1 pin 52 pin 53 pin 92 pin 144 pin 145 back view front view standard height pin 93 pin 184 pin 144 pin 145 pin 1 pin 52 pin 53 pin 92 front view 1u height back view
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules pin configuration data sheet 13 rev. 1.1, 2004-04 10102003-01e2-hpa8 table 6 address format density organization memory ranks sdrams # of sdrams # of row/bank/ columns bits refresh period interval 256 mb 32m x 72 1 32m 8 9 13 / 2 / 10 8k 64 ms 7.8 s 512 mb 64m 72 1 64m 4 18 13 / 2 / 11 8k 64 ms 7.8 s 512 mb 64m 72 2 32m 8 18 13 / 2 / 10 8k 64 ms 7.8 s 1gb 128m 72 2 64m 4 36 13 / 2 / 11 8k 64 ms 7.8 s
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules pin configuration data sheet 14 rev. 1.1, 2004-04 10102003-01e2-hpa8 figure 2 block diagram: one rank 32m 72 ddr sdram dimm module (32m 8 components) hys72d32300gbr on raw card a pck pck dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm d0 dm0/dqs9 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm d1 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm d2 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm d3 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm d4 dm4/dqs13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm d5 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm d6 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm d7 dm7/dqs16 rs 0 cs cs cs cs cs cs cs cs dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6/dqs15 dqs6 dqs7 dq15 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm i/o 7 i/o 6 i/o 1 i/o 0 d8 i/o 5 i/o 4 i/o 3 i/o 2 cs dqs8 dm8/dqs17 dqs dqs dqs dqs dqs ck0, ck 0 --------- pll* * wire per clock loading table/wiring diagrams cs0 rs 0 -> cs : sdrams d0-d8 ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d8 a0-a12 ra0-ra12 -> a0-a12: sdrams d0 - d8 ras rras -> ras : sdrams d0 - d8 cas rcas -> cas : sdrams d0 - d8 cke0 rcke0 -> cke: sdrams d0 - d8 we rwe -> we : sdrams d0 - d8 r e g i s t e r reset i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 notes: 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, adress and control resistors: 22 ohms. 4. vddid strap connections strap out (open): vdd = vddq 5. sdram placement alternates between the back and front of the dimm. v dd, v ss d0 - d8 d0 - d8 v ddq d0 - d8 d0 - d8 vref v ddid strap: see note 4 v ddspd eeprom a0 serial pd a1 a2 sa0 sa1 sa2 scl sda
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules pin configuration data sheet 15 rev. 1.1, 2004-04 10102003-01e2-hpa8 figure 3 block diagram: two ranks 64m 72 ddr-i sdram dimm module (32m 8 components) hys 72d64320gbr on raw card b dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm d0 dm0/dqs9 dm d9 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm d1 dm d10 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm d2 dm d11 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm d3 dm d12 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm d4 dm4/dqs13 dm d13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm d5 dm d14 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm d6 dm d15 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm d7 dm d16 dm7/dqs16 rs 0 rs 1 cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs2 dqs dqs dqs3 dqs dqs dm6/dqs15 dqs6 dqs7 dq15 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm d8 dm d17 cs cs dqs8 dm8/dqs17 dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs ck0, ck 0 --------- pll* * wire per clock loading table/wiring diagrams cs1 rs 1 -> cs : sdram d9-d17 ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d17 a0-a12 ra0-ra12 -> a0-a12: sdrams d0 - d17 ras rras -> ras : sdrams d0 - d17 cs0 rs 0 -> cs : sdram d0-d8 cas rcas -> cas : sdrams d0 - d17 cke0 rcke0 -> cke: sdrams d0 - d8 we rwe -> we : sdrams d0 - d17 r e g i s t e r rcke1 -> cke: sdrams d9 - d17 pck pck cke1 reset i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda notes: 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, adress and control resistors: 22 ohms. 4. vddid strap connections strap out (open): vdd = vddq 5. sdram placement alternates between the back and front of the dimm. v dd, v ss v ddq vref v ddid strap: see note 4 v ddspd eeprom d0 - d17 d0 - d17 d0 - d17
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules pin configuration data sheet 16 rev. 1.1, 2004-04 10102003-01e2-hpa8 figure 4 block diagram: one rank 64m 72 ddr-i sdram dimm modules (64m 4 components) hys72d64300gbr on raw card c rs 0a dqs4 dqs6 dqs2 dq0 dq1 dq2 dq3 dq8 dq9 dq10 dq11 dq16 dq17 dq18 dq19 dq24 dq25 dq26 dq27 dq32 dq33 dq34 dq35 dq40 dq41 dq42 dq43 dq56 dq57 dq58 dq59 dqs d0 dqs dqs dqs dqs dqs dqs dqs0 d1 d2 d3 d4 d5 d7 dq48 dq49 dq50 dq51 dqs d6 dq4 dq5 dq6 dq7 dq12 dq13 dq14 dq15 dq20 dq21 dq22 dq23 dq28 dq29 dq30 dq31 dq36 dq37 dq38 dq39 dq44 dq45 dq46 dq47 dq60 dq61 dq62 dq63 dqs d9 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dm0/dqs9 d10 d11 d12 d13 d14 d16 dq52 dq53 dq54 dq55 dqs i/o 0 i/o 1 i/o 2 i/o 3 d15 cb0 cb1 cb2 cb3 dqs d8 cb4 cb5 cb6 cb7 dqs i/o 0 i/o 1 i/o 2 i/o 3 d17 cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs vss dqs1 dqs3 dqs8 dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dqs5 dqs7 dm6/dqs15 dm5/dqs14 dm4/dqs13 dm1/dqs10 dm2/dqs11 dm3/dqs12 dm7/dqs16 dm8/dqs17 rs 0b ck0, ck 0 --------- pll* * wire per clock loading table/wiring diagrams ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d17 a0-a11,a12 ra0-ra11,ra12 -> a0-a11,a12: sdrams d0 - d17 ras rras -> ras : sdrams d0 - d17 cs0 cas rcas -> cas : sdrams d0 - d17 cke0 rcke0a -> cke: sdrams d0 - d8 we rwe -> we : sdrams d0 - d17 r e g i s t e r rckeb -> cke: sdrams d9 - d17 pck pck reset i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda notes: 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, adress and control resistors: 22 ohms. 4. vddid strap connections strap out (open): vdd = vddq 5. sdram placement alternates between the back and front of the dimm. v dd, v ss v ddq vref v ddid strap: see note 4 v ddspd eeprom d0 - d17 d0 - d17 d0 - d17 rs 0 -> cs : sdrams d0-d17
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules pin configuration data sheet 17 rev. 1.1, 2004-04 10102003-01e2-hpa8 figure 5 block diagram: two ranks 128m 72 ddr sdram dimm modules (64m 4 components) hys72d128320gbr on raw card d pck pck rs 0 dqs4 dqs6 dqs2 dq0 dq1 dq2 dq3 dq8 dq9 dq10 dq11 dq16 dq17 dq18 dq19 dq24 dq25 dq26 dq27 dq32 dq33 dq34 dq35 dq40 dq41 dq42 dq43 dq56 dq57 dq58 dq59 dqs d0 dqs dqs dqs dqs dqs dqs dqs0 d1 d2 d3 d4 d5 d7 dq48 dq49 dq50 dq51 dqs d6 dq4 dq5 dq6 dq7 dq12 dq13 dq14 dq15 dq20 dq21 dq22 dq23 dq28 dq29 dq30 dq31 dq36 dq37 dq38 dq39 dq44 dq45 dq46 dq47 dq60 dq61 dq62 dq63 dqs i/o 0 i/o 1 i/o 2 i/o 3 d9 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dm0/dqs9 d10 d11 d12 d13 d14 d16 dq52 dq53 dq54 dq55 dqs i/o 0 i/o 1 i/o 2 i/o 3 d15 ck0, ck 0 --------- pll* cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs s 1 rs 1 -> cs : sdrams d18-d35 ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d35 a0-a12 ra0-ra12 -> a0-a12: sdrams d0- d35 ras rras -> ras : sdrams d0-d35 s 0 rso -> cs : sdrams d0-d17 v ss dqs1 dqs3 dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dm dqs5 dqs7 dm6/dqs15 dm5/dqs14 dm4/dqs13 dm1/dqs10 dm2/dqs11 dm3/dqs12 dm7/dqs16 * wire per clock loading table/wiring diagrams v dd v ss d0-d35 d0-d35 v ddq d0-d35 d0-d35 vref rs 1 notes: 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq/dqs resistors should be 22 ohms. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq . 5. address and control resistors should be 22 ohms. 6. each chip select and cke pair alternate between decks for ther- mal enhancement. v ddid strap: see note 4 cas rcas -> cas : sdrams d0-d35 cke0 rcke0 -> cke: sdrams d0-d17 we rwe -> we : sdrams d0-d35 r e g i s t e r dqs i/o 3 i/o 2 i/o 1 i/o 0 d18 dqs dqs dqs dqs dqs dqs d19 d20 d21 d22 d23 d25 dqs d24 cs cs cs cs cs cs cs cs dm dm dm dm dm dm dm dm dqs i/o 0 i/o 1 i/o 2 i/o 3 d27 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 dqs i/o 0 i/o 1 i/o 2 i/o 3 d28 d29 d30 d31 d32 d34 dqs i/o 0 i/o 1 i/o 2 i/o 3 d33 cs cs cs cs cs cs cs cs dm dm dm dm dm dm dm dm cb0 cb1 cb2 cb3 dqs d8 cs dm dqs8 dqs d26 cs dm cb4 cb5 cb6 cb7 dqs i/o 0 i/o 1 i/o 2 i/o 3 d17 cs dm dm8/dqs17 dqs i/o 0 i/o 1 i/o 2 i/o 3 d35 cs dm reset cke1 rcke1 -> cke: sdrams d18-d35 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 v ddspd serial pd a0 serial pd a1 a2 sa0 sa1 sa2 sda scl wp
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules electrical characteristics data sheet 18 rev. 1.1, 2004-04 10102003-01e2-hpa8 3 electrical characteristics 3.1 operating conditions attention: permanent damage to the device may occur if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operation should be restricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. table 7 absolute maximum ratings parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v? voltage on inputs relative to v ss v in ?0.5 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?0.5 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?0.5 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg -55 ? +150 c? power dissipation (per sdram component) p d ?2.0?w? short circuit output current i out ?50?ma? table 8 electrical characteristics and dc operating conditions parameter symbol values unit note/test condition 1) min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 166 mhz device supply voltage v dd 2.5 2.6 2.7 v f ck >166mhz 2) output supply voltage v ddq 2.3 2.5 2.7 v f ck 166 mhz 3) output supply voltage v ddq 2.5 2.6 2.7 v f ck >166mhz 2)3) eeprom supply voltage v ddspd 2.3 2.5 3.6 v ? supply voltage, i/o supply voltage v ss , v ssq 00v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 4) i/o termination voltage (system) v tt v ref ? 0.04 v ref + 0.04 v 5) input high (logic1) voltage v ih(dc) v ref + 0.15 v ddq + 0.3 v 8) input low (logic0) voltage v il(dc) ?0.3 v ref ? 0.15 v 8) input voltage level, ck and ck inputs v in(dc) ?0.3 v ddq + 0.3 v 8) input differential voltage, ck and ck inputs v id(dc) 0.36 v ddq + 0.6 v 8)6) vi-matching pull-up current to pull-down current vi ratio 0.71 1.4 ? 7)
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules electrical characteristics data sheet 19 rev. 1.1, 2004-04 10102003-01e2-hpa8 input leakage current i i ?2 2 a any input 0 v v in v dd ; all other pins not under test =0v 8)9) output leakage current i oz ?5 5 a dqs are disabled; 0v v out v ddq output high current, normal strength driver i oh ??16.2ma v out = 1.95 v output low current, normal strength driver i ol 16.2 ? ma v out = 0.35 v 1) 0 c t a 70 c 2) ddr400 conditions apply for all clock frequencies above 166 mhz 3) under all conditions, v ddq must be less than or equal to v dd . 4) peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise variations in v ddq . 5) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 6) v id is the magnitude of the difference between the input level on ck and the input level on ck . 7) the ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 v. for a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) inputs are not recognized as valid until v ref stabilizes. 9) values are shown per ddr sdram component table 8 electrical characteristics and dc operating conditions (cont?d) parameter symbol values unit note/test condition 1) min. typ. max.
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules electrical characteristics data sheet 20 rev. 1.1, 2004-04 10102003-01e2-hpa8 table 9 i dd specifications product type & organisation hys72d32300gbr-5-b hys72d64300gbr-5-b hys72d64320gbr-5-b hys72d128320gbr-5-b unit note/ test conditions 5) 256 mb 72 1 rank ? 5 512 mb 72 1 rank ? 5 512 mb 72 2 ranks ? 5 1 gbyte 72 2 ranks ? 5 typ. max. typ. max. typ. max. typ. max. i dd0 1690 1960 2500 3040 2284 2599 3688 4318 ma 1)4) 1) the module i dd values are calculated from the component i dd datasheet values are: n * i dd [component] for single bank modules (n: number of components per module bank) n * i dd [component] + n * i dd3n [component] for two bank modules (n: number of components per module bank) i dd1 1825 2005 2770 3130 2419 2644 3958 4408 ma 1)3)4) i dd2p 698 725 752 806 752 806 860 968 ma 2)4) 2) the module i dd values are calculated from the component i dd datasheet values are: n * i dd [component] for single bank modules (n: number of components per module bank) 2 * n * i dd [component] for single two bank modules (n: number of components per module bank) i dd2f 1076 1139 1508 1634 1508 1634 2372 2624 ma 2)4) i dd2q 878 932 1112 1220 1112 1220 1580 1796 ma 2)4) i dd3p 815 869 986 1094 986 1094 1328 1544 ma 2)4) i dd3n 1238 1319 1832 1994 1832 1994 3020 3344 ma 2)4) i dd4r 2005 2185 3130 3490 2599 2824 4318 4768 ma 1)3)4) 3) dq i/o ( i ddq ) currents are not included into calculations: module i dd values will be measured differently depending on load conditions i dd4w 2005 2194 3130 3508 2599 2833 4318 4786 ma 1)4) i dd5 2320 2635 3760 4390 2914 3274 4948 5668 ma 1)4) 4) module i dd is calculated on the basis of component i dd and includes register and pll i dd6 656.6 671 669.2 698 669.2 698 694.4 752 ma 2)4) i dd7 3040 3310 5200 5740 3634 3949 6388 7018 ma 1)3)4) 5) 5) test condition for maximum values: v dd =2.7v, t a =10c
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules electrical characteristics data sheet 21 rev. 1.1, 2004-04 10102003-01e2-hpa8 table 10 i dd specifications product type & organisation hys72d32300gbr-6-b hys72d64300gbr-6-b hys72d64320gbr-6-b hys72d128320gbr-6-b unit note/ test conditions 5) 256 mb 72 1 rank ? 6 512 mb 72 1ranks ? 6 512 mb 72 2 ranks ? 6 1 gb 72 2 ranks ? 6 typ. max. typ. max. typ. max. typ. max. i dd0 1495 1720 2260 2710 2035 2305 3340 3880 ma 1)4) 1) the module i dd values are calculated from the component i dd datasheet values are: n * i dd [component] for single bank modules (n: number of components per module bank) n * i dd [component] + n * i dd3n [component] for two bank modules (n: number of components per module bank) i dd1 1630 1810 2530 2890 2170 2395 3610 4060 ma 1)3)4) i dd2p 484 511 538 592 538 592 646 754 ma 2)4) 2) the module i dd values are calculated from the component i dd datasheet values are: n * i dd [component] for single bank modules (n: number of components per module bank) 2 * n * i dd [component] for single two bank modules (n: number of components per module bank) i dd2f 835 925 1240 1420 1240 1420 2050 2410 ma 2)4) i dd2q 652 682 875 934 875 934 1319 1438 ma 2)4) i dd3p 592 619 754 808 754 808 1078 1186 ma 2)4) i dd3n 970 1015 1510 1600 1510 1600 2590 2770 ma 2)4) i dd4r 1720 1990 2710 3250 2260 2575 3790 4420 ma 1)3)4) 3) dq i/o ( i ddq ) currents are not included into calculations: module i dd values will be measured differently depending on load conditions i dd4w 1855 2035 2980 3340 2395 2620 4060 4510 ma 1)4) i dd5 2022 2440 3313 4150 2562 3025 4393 5320 ma 1)4) 4) module i dd is calculated on the basis of component i dd and includes register and pll i dd6 444 453 457 475 457 475 484 520 ma 2)4) i dd7 2600 3160 4470 5590 3140 3745 5550 6760 ma 1)3)4) 5) 5) test condition for maximum values: v dd =2.7v, t a =10c
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules electrical characteristics data sheet 22 rev. 1.1, 2004-04 10102003-01e2-hpa8 table 11 i dd specifications product type & organisation hys72d32300gbr-7-b hys72d64300gbr-7-b HYS72D64320GBR-7-B hys72d128320gbr-7-b unit note/ test conditions 5) 256 mb 72 1 rank ? 7 512 mb 72 1 rank ? 7 512 mb 72 2 ranks ? 7 1 gb 72 2 ranks ? 7 typ. max. typ. max. typ. max. typ. max. i dd0 1263 1488 1938 2388 1713 1983 2838 3378 ma 1)4) 1) the module i dd values are calculated from the component i dd datasheet values are: n * i dd [component] for single bank modules (n: number of components per module bank) n * i dd [component] + n * i dd3n [component] for two bank modules (n: number of components per module bank) i dd1 1398 1578 2208 2568 1848 2073 3108 3558 ma 1)3)4) i dd2p 426 448 475 520 475 520 574 664 ma 2)4) 2) the module i dd values are calculated from the component i dd datasheet values are: n * i dd [component] for single bank modules (n: number of components per module bank) 2 * n * i dd [component] for single two bank modules (n: number of components per module bank) i dd2f 691 736 1006 1096 1006 1096 1636 1816 ma 2)4) i dd2q 556 601 736 826 736 826 1096 1276 ma 2)4) i dd3p 511 538 646 700 646 700 916 1024 ma 2)4) i dd3n 826 871 1276 1366 1276 1366 2176 2356 ma 2)4) i dd4r 1443 1623 2298 2658 1893 2118 3198 3648 ma 1)3)4) 3) dq i/o ( i ddq ) currents are not included into calculations: module i dd values will be measured differently depending on load conditions i dd4w 1533 1713 2478 2838 1983 2208 3378 3828 ma 1)4) i dd5 1803 2208 3018 3828 2253 2703 3918 4818 ma 1)4) 4) module i dd is calculated on the basis of component i dd and includes register and pll i dd6 390 399 403 421 403 421 430 466 ma 2)4) i dd7 2128 2613 3668 4638 2578 3108 4568 5628 ma 1)3)4) 5) 5) test condition for maximum values: v dd =2.7v, t a =10c
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules electrical characteristics data sheet 23 rev. 1.1, 2004-04 10102003-01e2-hpa8 3.2 ac characteristics table 12 ac timing - absolute specifications ?5/?6/?7 parameter symbol ?5 ?6 ?7 unit note/ test condition 1) ddr400b ddr333 ddr266a min. max. min. max. min. max. dq output access time from ck/ck t ac ?0.7 +0.7 ?0.7 +0.7 ?0.75 +0.75 ns 2)3)4)5) dqs output access time from ck/ck t dqsck ?0.6 +0.6 ?0.6 +0.6 ?0.75 +0.75 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )min. ( t cl , t ch )min. ( t cl , t ch )ns 2)3)4)5) clock cycle time t ck 5 8 ? ? ? ? ns cl = 3.0 2)3)4)5) 6 12 6 12 7.5 12 ns cl = 2.5 2)3)4)5) 7.5 12 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) dq and dm input hold time t dh 0.4 ? 0.45 ? 0.5 ? ns 2)3)4)5) dq and dm input setup time t ds 0.4 ? 0.45 ? 0.5 ? ns 2)3)4)5) control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? 2.2 ? ns 2)3)4)5)6) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? 1.75 ? ns 2)3)4)5)6) data-out high-impedance time from ck/ck t hz ? +0.7 ? +0.7 ? +0.75 ns 2)3)4)5)7) data-out low-impedance time from ck/ck t lz ?0.7 +0.7 ?0.7 +0.7 ?0.75 +0.75 ns 2)3)4)5)7) write command to 1 st dqs latching transition t dqss 0.72 1.25 0.75 1.25 0.75 1.25 t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.4 ? +0.4 ? +0.5 ns tfbga 2)3)4)5) data hold skew factor t qhs ? +0.5 ? +0.55 +0.75 ns tfbga 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs ? t hp ? t qhs ? t hp ? t qhs ?ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? 0.35 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? 0.2 ? t ck 2)3)4)5) mode register set command cycle time t mrd 2?2?2? t ck 2)3)4)5) write preamble setup time t wpres 0?0?0?ns 2)3)4)5)8) write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 2)3)4)5)9) write preamble t wpre 0.25 ? 0.25 ? 0.25 ? t ck 2)3)4)5)
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules electrical characteristics data sheet 24 rev. 1.1, 2004-04 10102003-01e2-hpa8 address and control input setup time t is 0.6 ? 0.75 ? 0.9 ? ns fast slew rate 3)4)5)6)10) 0.7 ? 0.8 ? 1.0 ? ns slow slew rate 3)4)5)6)10) address and control input hold time t ih 0.6 0.75 ? 0.9 ? ns fast slew rate 3)4)5)6)10) 0.7 0.8 ? 1.0 ? ns slow slew rate 3)4)5)6)10) read preamble t rpre 0.9 1.1 0.9 1.1 0.90 1.1 t ck 2)3)4)5) read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 2)3)4)5) active to precharge command t ras 40 70e+3 42 70e+3 45 70e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 55 60 ? 65 ? ns 2)3)4)5) auto-refresh to active/auto- refresh command period t rfc 65 72 ? 75 ? ns 2)3)4)5) active to read or write delay t rcd 15 ? 18 ? 20 ? ns 2)3)4)5) precharge command period t rp 15 ? 18 ? 20 ? ns 2)3)4)5) active to autoprecharge delay t rap t rcd or t rasmin t rcd or t rasmin t rcd or t rasmin ?ns 2)3)4)5) active bank a to active bank b command t rrd 10 ? 12 ? 15 ? ns 2)3)4)5) write recovery time t wr 15 ? 15 ? 15 ? ns 2)3)4)5) auto precharge write recovery + precharge time t dal ??? t ck 2)3)4)5)11) internal write to read command delay t wtr 2?1?1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? 200 ? t ck 2)3)4)5) average periodic refresh interval t refi ? 7.8 ? 7.8 ? 7.8 s 2)3)4)5)12) 1) 0 c t a 70 c ; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400) 2) input slew rate 1 v/ns for ddr400, ddr333 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) these parameters guarantee device timing, but they are not necessarily tested on each device. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). table 12 ac timing - absolute specifications ?5/?6/?7 (cont?d) parameter symbol ?5 ?6 ?7 unit note/ test condition 1) ddr400b ddr333 ddr266a min. max. min. max. min. max.
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules electrical characteristics data sheet 25 rev. 1.1, 2004-04 10102003-01e2-hpa8 8) the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 9) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v oh(ac) and v ol(ac) . 11) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 12) a maximum of eight autorefresh commands can be posted to any given ddr sdram device.
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules spd contents data sheet 26 rev. 1.1, 2004-04 10102003-01e2-hpa8 4 spd contents table 13 spd codes for hys72d128320gbr?5, hys72d643[00/20]gbr?5 and hys72d32300gbr?5 product type & organization hys72d128320gbr?5?b hys72d64300gbr?5?b hys72d64320gbr?5?b hys72d32300gbr?5?b 1 gbyte 512 mb 512 mb 256 mb 72 72 72 72 2 ranks 1 rank 2 ranks 1 rank label code pc3200r?30331 pc3200r?30330 pc3200r?30330 pc3200r?30330 jedec spd revision rev 1.0 rev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex 0 programmed spd bytes in e2prom 80 80 80 80 1 total number of bytes in e2prom 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0b 0b 0a 0a 5 number of dimm ranks 02 01 02 01 6 data width (lsb) 48 48 48 48 7 data width (msb) 00 00 00 00 8 interface voltage levels 04 04 04 04 9 tck @ clmax (byte 18) [ns] 50 50 50 50 10 tac sdram @ clmax (byte 18) [ns] 50 50 50 50 11 error correction support 02 02 02 02 12 refresh rate 82 82 82 82 13 primary sdram width 04 04 08 08 14 error checking sdram width 04 04 08 08 15 tccd [cycles] 01 01 01 01
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules spd contents data sheet 27 rev. 1.1, 2004-04 10102003-01e2-hpa8 16 burst length supported 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 18 cas latency 1c 1c 1c 1c 19 cs latency 01 01 01 01 20 write latency 02 02 02 02 21 dimm attributes 26 26 26 26 22 component attributes c0 c1 c1 c1 23 tck @ clmax -0.5 (byte 18) [ns] 60 60 60 60 24 tac sdram @ clmax -0.5 [ns] 50 50 50 50 25 tck @ clmax -1 (byte 18) [ns] 75 75 75 75 26 tac sdram @ clmax -1 [ns] 50 50 50 50 27 trpmin [ns] 3c 3c 3c 3c 28 trrdmin [ns] 28 28 28 28 29 trcdmin [ns] 3c 3c 3c 3c 30 trasmin [ns] 28 28 28 28 31 module density per rank 80 80 40 40 32 tas, tcs [ns] 60 60 60 60 33 tah, tch [ns] 60 60 60 60 34 tds [ns] 40 40 40 40 35 tdh [ns] 40 40 40 40 36 - 40 not used 00 00 00 00 41 trcmin [ns] 37 37 37 37 table 13 spd codes for hys72d128320gbr?5, hys72d643[00/20]gbr?5 and hys72d32300gbr?5 product type & organization hys72d128320gbr?5?b hys72d64300gbr?5?b hys72d64320gbr?5?b hys72d32300gbr?5?b 1 gbyte 512 mb 512 mb 256 mb 72 72 72 72 2 ranks 1 rank 2 ranks 1 rank label code pc3200r?30331 pc3200r?30330 pc3200r?30330 pc3200r?30330 jedec spd revision rev 1.0 rev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules spd contents data sheet 28 rev. 1.1, 2004-04 10102003-01e2-hpa8 42 trfcmin [ns] 41 41 41 41 43 tckmax [ns] 28 28 28 28 44 tdqsqmax [ns] 28 28 28 28 45 tqhsmax [ns] 50 50 50 50 46 not used 00 00 00 00 47 dimm pcb height 01 00 00 00 48 - 61 not used 00 00 00 00 62 spd revision 10 00 00 00 63 checksum of byte 0- 62 5f 4e 16 15 64 jedec id code of infineon (1) c1 c1 c1 c1 65 jedec id code of infineon (2) 49 49 49 49 66 jedec id code of infineon (3) 4e 4e 4e 4e 67 jedec id code of infineon (4) 46 46 46 46 68 jedec id code of infineon (5) 49 49 49 49 69 jedec id code of infineon (6) 4e 4e 4e 4e 70 jedec id code of infineon (7) 45 45 45 45 71 jedec id code of infineon (8) 4f 4f 4f 4f 72 module manufacturer location xx xx xx xx 73 part number, char 1 37 37 37 37 74 part number, char 2 32 32 32 32 table 13 spd codes for hys72d128320gbr?5, hys72d643[00/20]gbr?5 and hys72d32300gbr?5 product type & organization hys72d128320gbr?5?b hys72d64300gbr?5?b hys72d64320gbr?5?b hys72d32300gbr?5?b 1 gbyte 512 mb 512 mb 256 mb 72 72 72 72 2 ranks 1 rank 2 ranks 1 rank label code pc3200r?30331 pc3200r?30330 pc3200r?30330 pc3200r?30330 jedec spd revision rev 1.0 rev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules spd contents data sheet 29 rev. 1.1, 2004-04 10102003-01e2-hpa8 75 part number, char 3 44 44 44 44 76 part number, char 4 31 36 36 33 77 part number, char 5 32 34 34 32 78 part number, char 6 38 33 33 33 79 part number, char 7 33 30 32 30 80 part number, char 8 32 30 30 30 81 part number, char 9 30 47 47 47 82 part number, char 10 47 42 42 42 83 part number, char 11 42 52 52 52 84 part number, char 12 52 35 35 35 85 part number, char 13 37 42 42 42 86 part number, char 14 42 20 20 20 87 part number, char 15 20 20 20 20 88 part number, char 16 20 20 20 20 89 part number, char 17 20 20 20 20 90 part number, char 18 20 20 20 20 91 module revision code xx xx xx xx 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 module serial number (1) xx xx xx xx 96 module serial number (2) xx xx xx xx 97 module serial number (3) xx xx xx xx table 13 spd codes for hys72d128320gbr?5, hys72d643[00/20]gbr?5 and hys72d32300gbr?5 product type & organization hys72d128320gbr?5?b hys72d64300gbr?5?b hys72d64320gbr?5?b hys72d32300gbr?5?b 1 gbyte 512 mb 512 mb 256 mb 72 72 72 72 2 ranks 1 rank 2 ranks 1 rank label code pc3200r?30331 pc3200r?30330 pc3200r?30330 pc3200r?30330 jedec spd revision rev 1.0 rev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules spd contents data sheet 30 rev. 1.1, 2004-04 10102003-01e2-hpa8 98 module serial number (4) xx xx xx xx 99 - 127 not used 00 00 00 00 table 14 spd codes for hys72d128320gbr?6?b, hys72d64300gbr?[6/7]?b, hys72d64320gbr?6?b and hys72d32300gbr?6?b product type & organization hys72d128320gbr?6?b hys72d64300gbr?6?b hys72d64300gbr?7?b hys72d64320gbr?6?b hys72d32300gbr?6?b 1 gbyte 512 mb 512 mb 512 mb 256 mb 72 72 72 72 72 2 ranks 1 rank 1 rank 2 ranks 1 rank label code pc2700r? 25330 pc2700r? 25330 pc2100r? 20330 pc2700r? 25330 pc2700r? 25330 jedec spd revision rev 0.0 rev 0.0 rev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex hex 0 programmed spd bytes in e2prom 80 80 80 80 80 1 total number of bytes in e2prom 08 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 07 table 13 spd codes for hys72d128320gbr?5, hys72d643[00/20]gbr?5 and hys72d32300gbr?5 product type & organization hys72d128320gbr?5?b hys72d64300gbr?5?b hys72d64320gbr?5?b hys72d32300gbr?5?b 1 gbyte 512 mb 512 mb 256 mb 72 72 72 72 2 ranks 1 rank 2 ranks 1 rank label code pc3200r?30331 pc3200r?30330 pc3200r?30330 pc3200r?30330 jedec spd revision rev 1.0 rev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules spd contents data sheet 31 rev. 1.1, 2004-04 10102003-01e2-hpa8 3 number of row addresses 0d 0d 0d 0d 0d 4 number of column addresses 0b 0b 0b 0a 0a 5 number of dimm ranks 02 01 01 02 01 6 data width (lsb) 48 48 48 48 48 7 data width (msb) 00 00 00 00 00 8 interface voltage levels 04 04 04 04 04 9 tck @ clmax (byte 18) [ns] 60 60 70 60 60 10 tac sdram @ clmax (byte 18) [ns] 70 70 75 70 70 11 error correction support 02 02 02 02 02 12 refresh rate 82 82 82 82 82 13 primary sdram width 04 04 04 08 08 14 error checking sdram width 04 04 04 08 08 15 tccd [cycles] 01 01 01 01 01 16 burst length supported 0e 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 04 table 14 spd codes for hys72d128320gbr?6?b, hys72d64300gbr?[6/7]?b, hys72d64320gbr?6?b and hys72d32300gbr?6?b product type & organization hys72d128320gbr?6?b hys72d64300gbr?6?b hys72d64300gbr?7?b hys72d64320gbr?6?b hys72d32300gbr?6?b 1 gbyte 512 mb 512 mb 512 mb 256 mb 72 72 72 72 72 2 ranks 1 rank 1 rank 2 ranks 1 rank label code pc2700r? 25330 pc2700r? 25330 pc2100r? 20330 pc2700r? 25330 pc2700r? 25330 jedec spd revision rev 0.0 rev 0.0 rev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex hex
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules spd contents data sheet 32 rev. 1.1, 2004-04 10102003-01e2-hpa8 18 cas latency 0c 0c 0c 0c 0c 19 cs latency 01 01 01 01 01 20 write latency 02 02 02 02 02 21 dimm attributes 26 26 26 26 26 22 component attributes c0 c0 c0 c0 c0 23 tck @ clmax - 0.5 (byte 18) [ns] 75 75 75 75 75 24 tac sdram @ clmax -0.5 [ns] 70 70 75 70 70 25 tck @ clmax -1 (byte 18) [ns] 00 00 00 00 00 26 tac sdram @ clmax -1 [ns] 00 00 00 00 00 27 trpmin [ns] 48 48 50 48 48 28 trrdmin [ns] 30 30 3c 30 30 29 trcdmin [ns] 48 48 50 48 48 30 trasmin [ns] 2a 2a 2d 2a 2a 31 module density per rank 80 80 80 40 40 32 tas, tcs [ns] 75 75 90 75 75 33 tah, tch [ns] 75 75 90 75 75 34 tds [ns] 45 45 50 45 45 35 tdh [ns] 45 45 50 45 45 36 - 40 not used 00 00 00 00 00 41 trcmin [ns] 3c 3c 41 3c 3c 42 trfcmin [ns] 48 48 4b 48 48 table 14 spd codes for hys72d128320gbr?6?b, hys72d64300gbr?[6/7]?b, hys72d64320gbr?6?b and hys72d32300gbr?6?b product type & organization hys72d128320gbr?6?b hys72d64300gbr?6?b hys72d64300gbr?7?b hys72d64320gbr?6?b hys72d32300gbr?6?b 1 gbyte 512 mb 512 mb 512 mb 256 mb 72 72 72 72 72 2 ranks 1 rank 1 rank 2 ranks 1 rank label code pc2700r? 25330 pc2700r? 25330 pc2100r? 20330 pc2700r? 25330 pc2700r? 25330 jedec spd revision rev 0.0 rev 0.0 rev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex hex
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules spd contents data sheet 33 rev. 1.1, 2004-04 10102003-01e2-hpa8 43 tckmax [ns] 30 30 30 30 30 44 tdqsqmax [ns] 28 28 32 28 28 45 tqhsmax [ns] 50 50 75 50 50 46 not used 00 00 00 00 00 47 dimm pcb height 00 00 00 00 00 48 - 61 not used 00 00 00 00 00 62 spd revision 00 00 00 00 00 63 checksum of byte 0-62 48 47 03 0f 0e 64 jedec id code of infineon (1) c1 c1 c1 c1 c1 65 jedec id code of infineon (2) 49 49 49 49 49 66 jedec id code of infineon (3) 4e 4e 4e 4e 4e 67 jedec id code of infineon (4) 46 46 46 46 46 68 jedec id code of infineon (5) 49 49 49 49 49 69 jedec id code of infineon (6) 4e 4e 4e 4e 4e 70 jedec id code of infineon (7) 45 45 45 45 45 71 jedec id code of infineon (8) 4f 4f 4f 4f 4f 72 module manufacturer location xx xx xx xx xx table 14 spd codes for hys72d128320gbr?6?b, hys72d64300gbr?[6/7]?b, hys72d64320gbr?6?b and hys72d32300gbr?6?b product type & organization hys72d128320gbr?6?b hys72d64300gbr?6?b hys72d64300gbr?7?b hys72d64320gbr?6?b hys72d32300gbr?6?b 1 gbyte 512 mb 512 mb 512 mb 256 mb 72 72 72 72 72 2 ranks 1 rank 1 rank 2 ranks 1 rank label code pc2700r? 25330 pc2700r? 25330 pc2100r? 20330 pc2700r? 25330 pc2700r? 25330 jedec spd revision rev 0.0 rev 0.0 rev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex hex
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules spd contents data sheet 34 rev. 1.1, 2004-04 10102003-01e2-hpa8 73 part number, char 1 37 37 37 37 37 74 part number, char 2 32 32 32 32 32 75 part number, char 3 44 44 44 44 44 76 part number, char 4 31 36 36 36 33 77 part number, char 5 32 34 34 34 32 78 part number, char 6 38 33 33 33 33 79 part number, char 7 33 30 30 32 30 80 part number, char 8 32 30 30 30 30 81 part number, char 9 30 47 47 47 47 82 part number, char 10 47 42 42 42 42 83 part number, char 11 42 52 52 52 52 84 part number, char 12 52 36 37 36 36 85 part number, char 13 36 42 42 42 42 86 part number, char 14 42 20 20 20 20 table 14 spd codes for hys72d128320gbr?6?b, hys72d64300gbr?[6/7]?b, hys72d64320gbr?6?b and hys72d32300gbr?6?b product type & organization hys72d128320gbr?6?b hys72d64300gbr?6?b hys72d64300gbr?7?b hys72d64320gbr?6?b hys72d32300gbr?6?b 1 gbyte 512 mb 512 mb 512 mb 256 mb 72 72 72 72 72 2 ranks 1 rank 1 rank 2 ranks 1 rank label code pc2700r? 25330 pc2700r? 25330 pc2100r? 20330 pc2700r? 25330 pc2700r? 25330 jedec spd revision rev 0.0 rev 0.0 rev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex hex
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules spd contents data sheet 35 rev. 1.1, 2004-04 10102003-01e2-hpa8 87 part number, char 15 20 20 20 20 20 88 part number, char 16 20 20 20 20 20 89 part number, char 17 20 20 20 20 20 90 part number, char 18 20 20 20 20 20 91 module revision code xx xx xx xx xx 92 test program revision code xx xx xx xx xx 93 module manufacturing date year xx xx xx xx xx 94 module manufacturing date week xx xx xx xx xx 95 module serial number (1) xx xx xx xx xx 96 module serial number (2) xx xx xx xx xx 97 module serial number (3) xx xx xx xx xx 98 module serial number (4) xx xx xx xx xx 99 - 127 not used 00 00 00 00 00 table 14 spd codes for hys72d128320gbr?6?b, hys72d64300gbr?[6/7]?b, hys72d64320gbr?6?b and hys72d32300gbr?6?b product type & organization hys72d128320gbr?6?b hys72d64300gbr?6?b hys72d64300gbr?7?b hys72d64320gbr?6?b hys72d32300gbr?6?b 1 gbyte 512 mb 512 mb 512 mb 256 mb 72 72 72 72 72 2 ranks 1 rank 1 rank 2 ranks 1 rank label code pc2700r? 25330 pc2700r? 25330 pc2100r? 20330 pc2700r? 25330 pc2700r? 25330 jedec spd revision rev 0.0 rev 0.0 rev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex hex
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules spd contents data sheet 36 rev. 1.1, 2004-04 10102003-01e2-hpa8 table 15 spd codes for hys72d[64/128]320gbr?7?b and hys72d32300gbr?7?b product type & organization hys72d128320gbr?7?b hys72d64320gbr?7?b hys72d32300gbr?7?b 1 gbyte 512 mb 256 mb 72 72 72 2 ranks 2 ranks 1 rank label code pc2100r? 20330 pc2100r? 20330 pc2100r? 20330 jedec spd revision rev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex 0 programmed spd bytes in e2prom 80 80 80 1 total number of bytes in e2prom 08 08 08 2 memory type (ddr = 07h) 07 07 07 3 number of row addresses 0d 0d 0d 4 number of column addresses 0b 0a 0a 5 number of dimm ranks 02 02 01 6 data width (lsb) 48 48 48 7 data width (msb) 00 00 00 8 interface voltage levels 04 04 04 9 tck @ clmax (byte 18) [ns] 70 70 70 10 tac sdram @ clmax (byte 18) [ns] 75 75 75 11 error correction support 02 02 02 12 refresh rate 82 82 82 13 primary sdram width 04 08 08 14 error checking sdram width 04 08 08 15 tccd [cycles] 01 01 01 16 burst length supported 0e 0e 0e 17 number of banks on sdram device 04 04 04 18 cas latency 0c 0c 0c 19 cs latency 01 01 01 20 write latency 02 02 02 21 dimm attributes 26 26 26 22 component attributes c0 c0 c0 23 tck @ clmax -0.5 (byte 18) [ns] 75 75 75 24 tac sdram @ clmax -0.5 [ns] 75 75 75 25 tck @ clmax -1 (byte 18) [ns] 00 00 00
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules spd contents data sheet 37 rev. 1.1, 2004-04 10102003-01e2-hpa8 26 tac sdram @ clmax -1 [ns] 00 00 00 27 trpmin [ns] 50 50 50 28 trrdmin [ns] 3c 3c 3c 29 trcdmin [ns] 50 50 50 30 trasmin [ns] 2d 2d 2d 31 module density per rank 80 40 40 32 tas, tcs [ns] 90 90 90 33 tah, tch [ns] 90 90 90 34 tds [ns] 50 50 50 35 tdh [ns] 50 50 50 36 - 40 not used 00 00 00 41 trcmin [ns] 41 41 41 42 trfcmin [ns] 4b 4b 4b 43 tckmax [ns] 30 30 30 44 tdqsqmax [ns] 32 32 32 45 tqhsmax [ns] 75 75 75 46 not used 00 00 00 47 dimm pcb height 00 00 00 48 - 61 not used 00 00 00 62 spd revision 00 00 00 63 checksum of byte 0-62 04 cb ca 64 jedec id code of infineon (1) c1 c1 c1 65 jedec id code of infineon (2) 49 49 49 66 jedec id code of infineon (3) 4e 4e 4e 67 jedec id code of infineon (4) 46 46 46 68 jedec id code of infineon (5) 49 49 49 69 jedec id code of infineon (6) 4e 4e 4e table 15 spd codes for hys72d[64/128]320gbr?7?b and hys72d32300gbr?7?b product type & organization hys72d128320gbr?7?b hys72d64320gbr?7?b hys72d32300gbr?7?b 1 gbyte 512 mb 256 mb 72 72 72 2 ranks 2 ranks 1 rank label code pc2100r? 20330 pc2100r? 20330 pc2100r? 20330 jedec spd revision rev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules spd contents data sheet 38 rev. 1.1, 2004-04 10102003-01e2-hpa8 70 jedec id code of infineon (7) 45 45 45 71 jedec id code of infineon (8) 4f 4f 4f 72 module manufacturer location xx xx xx 73 part number, char 1 37 37 37 74 part number, char 2 32 32 32 75 part number, char 3 44 44 44 76 part number, char 4 31 36 33 77 part number, char 5 32 34 32 78 part number, char 6 38 33 33 79 part number, char 7 33 32 30 80 part number, char 8 32 30 30 81 part number, char 9 30 47 47 82 part number, char 10 47 42 42 83 part number, char 11 42 52 52 84 part number, char 12 52 37 37 85 part number, char 13 37 42 42 86 part number, char 14 42 20 20 87 part number, char 15 20 20 20 88 part number, char 16 20 20 20 89 part number, char 17 20 20 20 90 part number, char 18 20 20 20 91 module revision code xx xx xx 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 module serial number (1) xx xx xx 96 module serial number (2) xx xx xx table 15 spd codes for hys72d[64/128]320gbr?7?b and hys72d32300gbr?7?b product type & organization hys72d128320gbr?7?b hys72d64320gbr?7?b hys72d32300gbr?7?b 1 gbyte 512 mb 256 mb 72 72 72 2 ranks 2 ranks 1 rank label code pc2100r? 20330 pc2100r? 20330 pc2100r? 20330 jedec spd revision rev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules spd contents data sheet 39 rev. 1.1, 2004-04 10102003-01e2-hpa8 97 module serial number (3) xx xx xx 98 module serial number (4) xx xx xx 99 - 127 not used 00 00 00 table 15 spd codes for hys72d[64/128]320gbr?7?b and hys72d32300gbr?7?b product type & organization hys72d128320gbr?7?b hys72d64320gbr?7?b hys72d32300gbr?7?b 1 gbyte 512 mb 256 mb 72 72 72 2 ranks 2 ranks 1 rank label code pc2100r? 20330 pc2100r? 20330 pc2100r? 20330 jedec spd revision rev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules package outlines data sheet 40 rev. 1.1, 2004-04 10102003-01e2-hpa8 5 package outlines figure 6 package outlines raw card a l-dim 184-21 6.35 0.1 2.5 0.1 4 0.1 1 6.62 95 64.77 ?0.1 a bc 1.27 x= 120.65 2.175 a c a b 128.95 133.35 b 49.53 92 28.58 0.13 0.15 b a c 2.64 max. 1.27 0.4 c 0.1 0.13 detail of contacts 0.2 1.27 0.2 0.05 1 0.1 a 2.5 93 3.8 c b 17.8 10 184 burr max. 0.4 allowed 3 min. 0.1 1.8 b a 0.1 c
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules package outlines data sheet 41 rev. 1.1, 2004-04 10102003-01e2-hpa8 figure 7 package outlines raw card b l-dim 184-23 4 max. 1.27 c 0.1 0.4 0.1 ?0.1 0.1 2.5 0.1 4 1 x 95 c 64.77 ab 120.65 1.27 = 2.175 6.35 a b c a 133.35 128.95 49.53 92 0.15 c ab 0.13 b 28.58 b a 0.1 c 1.8 c 1 b 0.1 a detail of contacts 0.2 1.27 3.8 0.13 93 0.2 2.5 0.05 17.8 184 10 0.1 3 min. burr max. 0.4 allowed 6.62
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules package outlines data sheet 42 rev. 1.1, 2004-04 10102003-01e2-hpa8 figure 8 package outline raw card c l-dim 184-22 128.95 2.5 1 64.77 ?0.1 0.1 a bc 4 0.1 0.1 a 120.65 6.35 1.27 95 x = 2.175 49.53 a c b 133.35 92 b 0.13 28.58 0.15 b a c 0.13 0.05 1 1.27 0.1 ab c detail of contacts 0.2 2.5 0.2 3.8 93 1.8 0.1 c 0.1 ab 17.8 184 10 1.27 0.4 c 0.1 4 max. burr max. 0.4 allowed 3 min. 6.62
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules package outlines data sheet 43 rev. 1.1, 2004-04 10102003-01e2-hpa8 figure 9 package outline raw card d l-dim 184-24 1 92 93 184 17.8 10 3.8 0.13 3 min. a 0.1 1.8 0.1 c b 0.05 1 1.27 c a 0.1 b 0.2 detail of contacts 2.5 0.2 a 4 0.1 0.1 bc 0.1 2.5 ?0.1 abc 6.62 2.175 1.27 64.77 95 x 120.65 = 6.35 49.53 b 0.13 30.48 128.95 a a 133.35 0.15 a bc 4 max. 1.27 0.4 c 0.1 burr max. 0.4 allowed
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules application note data sheet 44 rev. 1.1, 2004-04 10102003-01e2-hpa8 6 application note power up and power management on ddr registered dimms (according to jedec ballot jc-42.5 item 1173) 184-pin double data rate (ddr) regist ered dimms include two new features to facilitate controlled power-up and to minimize power consumption during low power mode. one feature is externally controlled via a system- generated reset signal; the second is based on module detection of the input clocks. these enhancements permit the modules to power up with sdram outputs in a high-z state (eliminating risk of high current dissipations and/or dotted i/os), and result in the powering-down of module support devices (registers and phase-locked loop) when the memory is in self-refresh mode. the new reset pin controls power dissipation on the module?s registers and ensures that cke and other sdram inputs are maintained at a valid ?low? level during power-up and self refresh. when reset is at a low level, all the register outputs are forced to a low level, and all differential register input receivers are powered down, resulting in very low register power consumption. the reset pin, located on dimm tab #10, is driven from the system as an asynchronous signal according to the attached details. using this function also permits the system and dimm clocks to be stopped during memory self refresh operation, while ensuring that the sdrams stay in self refresh mode. as described in the table above, a low on the reset input ensures that the clock enable (cke) signal(s) are maintained low at the sdram pins (cke being one of the 'q' signals at the register output). holding cke low maintains a high impedance state on the sdram dq, dqs and dm outputs ? where they will remain until activated by a valid ?read? cycle. cke low also maintains sdrams in self refresh mode when applicable. the ddr pll devices automatically detect clock activity above 20mhz. when an input clock frequency of 20mhz or greater is detected, the pll begins operation and initiates clock frequency lock (the minimum operating frequency at which all specifications will be met is 95mhz). if the clock input frequency drops below 20mhz (actual detect frequency will vary by vendor), the pll vco (voltage controlled oscillator) is stopped, outputs are made high-z, and the differential inputs are powered down ? resulting in a total pll current consumption of less than 1ma. use of this low power pll function makes the use of the pll reset (or g pin) unnecessary, and it is tied inactive on the dimm. this application note describes the required and optional system sequences associated with the ddr registered dimm 'reset ' function. it is important to note that all references to cke refer to both cke0 and cke1 for a 2- bank dimm. because reset applies to all dimm register devices, it is therefore not possible to uniquely control cke to one physical dimm bank through the use of the reset pin. table 16 reset truth table register inputs register outputs reset ck ck data in (d) data out (q) h rising falling h h h rising falling l l h l or h l or h x qo h high z high z x illegal input conditions l x or hi-z x or hi-z x or hi-z l x: don?t care, hi-z: high impedance, qo: data latched at the previous of ck rising and ck falling
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules application note data sheet 45 rev. 1.1, 2004-04 10102003-01e2-hpa8 power-up sequence with reset ? required 1. the system sets reset at a valid low level. this is the preferred default state during power-up. this input condition forces all register outputs to a low state independent of the condition on the register inputs (data and clock), ensuring that cke is at a stable low-level at the ddr sdrams. 2. the power supplies should be initialized according to the jedec-approved initialization sequence for ddr sdrams. 3. stabilization of clocks to the sdram the system must drive clocks to the application frequency (pll operation is not assured until the input clock reaches 20 mhz). stability of clocks at the sdrams will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. once a stable clock is received at the dimm pll, the required pll stabilization time (assuming power to the dimm is stable) is 100 microseconds. when a stable clock is present at the sdram input (driven from the pll), the ddr sdram requires 200 sec prior to sdram operation. 4. the system applies valid logic levels to the data inputs of the register (address and controls at the dimm connector). cke must be maintained low and all other inputs should be driven to a known state. in general these commands can be determined by the system designer. one option is to apply an sdram ?nop? command (with cke low), as this is the first command defined by the jedec initialization sequence (ideally this would be a ?nop deselect? command). a second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 5. the system switches reset to a logic ?high? level. the sdram is now functional and prepared to receive commands. since the reset signal is asynchronous, setting the reset timing in relation to a specific clock edge is not required (during this period, register inputs must remain stable). 6. the system must maintain stable register inputs until normal register operation is attained. the registers have an activation time that allows their clock receivers, data input receivers, and output drivers sufficient time to be turned on and become stable. during this time the system must maintain the valid logic levels described in step 5. it is also a functional requirement that the registers maintain a low state at the cke outputs to guarantee that the ddr sdrams continue to receive a low level on cke. register activation time ( t (act) ), from asynchronous switching of reset from low to high until the registers are stable and ready to accept an input signal, is specified in the register and dimm do-umentation. 7. the system can begin the jedec-defined ddr sdram power-up sequence (according to the jedec- pproved initialization sequence). self refresh entry (reset low, clocks powered off) ? optional self refresh can be used to retain data in ddr sdram dimms even if the rest of the system is powered down and the clocks are off. this mode allows the ddr sdrams on the dimm to retain data without external clocking. self refresh mode is an ideal time to utilize the reset pin, as this can reduce register power consumption (reset low deactivates register ck and ck, data input receivers, and data output drivers). 1. 1. the system applies self refresh entry command. (cke low, cs low, ras low, cas low, we high) note: note: the commands reach the ddr sdram one clock later due to the additional register pipelining on a registered dimm. after this command is issued to the sdram, all of the address and control and clock input conditions to the sdram are don?t cares? with the exception of cke. 2. the system sets reset at a valid low level. this input condition forces all register outputs to a low state, independent of the condition on the registerm inputs (data and clock), and ensures that cke, and all other control and address signals, are a stable low-level at the ddr sdrams. since the reset signal is asynchronous, setting the reset timing in relation to a specific clock edge is not required. 3. the system turns off clock inputs to the dimm. (optional) a. in order to reduce dimm pll current, the clock inputs to the dimm are turned off, resulting in high-z clock
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules application note data sheet 46 rev. 1.1, 2004-04 10102003-01e2-hpa8 inputs to both the sdrams and the registers. this must be done after the reset deactivate time of the register (t (inact) . the deactivate time defines the time in which the clocks and the control and address signals must maintain valid levels after reset low has been applied and is specified in the register and dimm documentation. b.the system may release dimm address and control inputs to high-z. this can be done after the reset deactivate time of the register. the deactivate time defines the time in which the clocks and the control and the address signals must maintain valid levels after reset low has been applied. it is highly recommended that cke continue to remain low during this operation. 4. the dimm is in lowest power self refresh mode. self refresh exit (reset low, clocks powered off) ? optional 1. stabilization of clocks to the sdram. the system must drive clocks to the application frequency (pll operation is not assured until the input clock reaches ~20mhz). stability of clocks at the sdrams will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. once a stable clock is received at the dimm pll, the required pll stabilization time (assuming power to the dimm is stable) is 100 microseconds. 2. the system applies valid logic levels to the data inputs of the register (address and controls at the dimm connector). cke must be maintained low and all other inputs should be driven to a known state. in general these commands can be determined by the system designer. one option is to apply an sdram ?nop? command (with cke low), as this is the first command defined by the jedec self refresh exit sequence (ideally this would be a ?nop deselect? command). a second option is to apply low levels on all of the register inputs, to be consistent with the state of the register outputs. 3. the system switches reset to a logic ?high? level. the sdram is now functional and prepared to receive commands. since the reset signal is asynchronous, reset timing relationship to a specific clock edge is not required (during this period, register inputs must remain stable). 4. the system must maintain stable register inputs until normal register operation is attained. the registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. during this time the system must maintain the valid logic levels described in step 2. it is also a functional requirement that the registers maintain a low state at the cke outputs to guarantee that the ddr sdrams continue to receive a low level on cke. register activation time (t (act) ), from asynchronous switching of reset from low to high until the registers are stable and ready to accept an input signal, is specified in the register and dimm do-umentation. 5. system can begin the jedec-defined ddr sdram self refresh exit procedure. self refresh entry (reset low, clocks running) ? optional although keeping the clocks running increases power consumption from the on-dimm pll during self refresh, this is an alternate operating mode for these dimms. 1. 1. system enters self refresh entry command. (cke low, cs low, ras low, cas low, we high) note: note: the commands reach the ddr sdram one clock later due to the additional register pipelining on a registered dimm. after this command is issued to the sdram, all of the address and control and clock input conditions to the sdram are don?t cares ? with the exception of cke. 2. the system sets reset at a valid low level. this input condition forces all register outputs to a low state, independent of the condition on the data and clock register inputs, and ensures that cke is a stable low-level at the ddr sdrams. 3. the system may release dimm address and control inputs to high-z. this can be done after the reset deactivate time of the register (t (inact) ). the deactivate time describes the time in which the clocks and the control and the address signals must maintain valid levels after reset low has been applied. it is highly recommended that cke continue to remain low during the operation. 4. the dimm is in a low power, self refresh mode.
hys72d[32/64/128]3[00/20]gbr registered double da ta rate sdram modules application note data sheet 47 rev. 1.1, 2004-04 10102003-01e2-hpa8 self refresh exit (reset low, clocks running) ? optional 1. the system applies valid logic levels to the data inputs of the register (address and controls at the dimm connector). cke must be maintained low and all other inputs should be driven to a known state. in general these commands can be determined by the system designer. one option is to apply an sdram ?nop? command (with cke low), as this is the first command defined by the self refresh exit sequence (ideally this would be a ?nop deselect? command). a second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 2. the system switches reset to a logic 'high' level. the sdram is now functional and prepared to receive commands. since the reset signal is asynchronous, it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain stable). 3. the system must maintain stable register inputs until normal register operation is attained. the registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. during this time the system must maintain the valid logic levels described in step 1. it is also a functional requirement that the registers maintain a low state at the cke outputs in order to guarantee that the ddr sdrams continue to receive a low level on cke. this activation time, from asynchronous switching of reset from low to high, until the registers are stable and ready to accept an input signal, is t (act ) as specified in the register and dimm documentation. 4. the system can begin jedec defined ddr sdram self refresh exit procedure. self refresh entry/exit (reset high, clocks running) ? optional as this sequence does not involve the use of the reset function, the jedec standard sdram specification explains in detail the method for entering and exiting self refresh for this case. self refresh entry (reset high, clocks powered off) ? not permissible in order to maintain a valid low level on the register output, it is required that either the clocks be running and the system drive a low level on cke, or the clocks are powered off and reset is asserted low according to the sequence defined in this application note . in the case where reset remains high and the clocks are powered off, the pll drives a high-z clock input into the register clock input. without the low level on reset an unknown dimm state will result.
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